Cost-efficient SHA hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compact Implementation of SHA-1 Hash Function for Mobile Trusted Module
Information Security Applications
Power efficient hardware architecture of SHA-1 algorithm for trusted mobile computing
ICICS'07 Proceedings of the 9th international conference on Information and communications security
High-throughput implementation of the RIPEMD-160
International Journal of Internet Technology and Secured Transactions
Improving SHA-2 hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
ATC'07 Proceedings of the 4th international conference on Autonomic and Trusted Computing
Hardware performance optimization and evaluation of SM3 hash algorithm on FPGA
ICICS'12 Proceedings of the 14th international conference on Information and Communications Security
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Hash functions are widely used in applications that call for data integrity and signature authentication at electronic transactions. A hash function is utilized in the security layer of every communication protocol. As time passes more sophisticated applications arise that address to more users-clients and thus demand for higher throughput. Furthermore, due to the tendency of the market to minimize devices' size and increase their autonomy to make them portable, power issues have also to be considered. The existing SHA-1 Hash Function implementations (SHA-1 is common in many protocols e.g. IPSec) limit throughput to a maximum of 2 Gbps. In this paper, a new implementation comes to exceed this limit improving the throughput by 53%. Furthermore,power dissipation is kept low compared to previous works, in such way that the proposed implementation can be characterized as low-power.