Optimizing SHA-1 hash function for high throughput with a partial unrolling study
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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The Mobile Trusted Platform (MTP) is developed and promoted by the Trusted Computing Group (TCG), which is an industry standard body to enhance the security of the mobile computing environment. The dedicated SHA-1 and HMAC engine in Mobile Trusted Module (MTM) are one of the most important circuit blocks and contribute the performance of the whole platform because they are used as key primitives verifying platform code, integrity and command authentication. Unlike desktop computers, mobile devices have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for low power SHA-1 and HMAC circuit are required. In this paper, we present a compact and efficient hardware architecture of low power SHA-1 and HMAC design for MTM. Our SHA-1 hardware can compute 512-bit data block using about 8,200 gates and has a power consumption about 1.1 mA on a 0.25µm CMOS process. The implementation of HMAC using the SHA-1 circuit requires additional 8,100 gates and consumes about 2.58 mA on the same process.