Secure electronic transactions: introduction and technical reference
Secure electronic transactions: introduction and technical reference
Arithmetic optimization using carry-save-adders
DAC '98 Proceedings of the 35th annual Design Automation Conference
IPSec
An FPGA Based SHA-256 Processor
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Overview of IEEE 802.16 Security
IEEE Security and Privacy
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Implementation of the SHA-2 Hash Family Standard Using FPGAs
The Journal of Supercomputing
Optimisation of the SHA-2 Family of Hash Functions on FPGAs
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Multi-mode operator for SHA-2 hash functions
Journal of Systems Architecture: the EUROMICRO Journal
A Reconfigurable Implementation of the New Secure Hash Algorithm
ARES '07 Proceedings of the The Second International Conference on Availability, Reliability and Security
Cost-efficient SHA hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
Integration, the VLSI Journal
A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores
IEEE Transactions on Dependable and Secure Computing
Power efficient hardware architecture of SHA-1 algorithm for trusted mobile computing
ICICS'07 Proceedings of the 9th international conference on Information and communications security
Improving SHA-2 hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Finding collisions in the full SHA-1
CRYPTO'05 Proceedings of the 25th annual international conference on Advances in Cryptology
ATC'07 Proceedings of the 4th international conference on Autonomic and Trusted Computing
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High-throughput and area-efficient designs of hash functions and corresponding mechanisms for Message Authentication Codes (MACs) are in high demand due to new security protocols that have arisen and call for security services in every transmitted data packet. For instance, IPv6 incorporates the IPSec protocol for secure data transmission. However, the IPSec's performance bottleneck is the HMAC mechanism which is responsible for authenticating the transmitted data. HMAC's performance bottleneck in its turn is the underlying hash function. In this article a high-throughput and small-size SHA-256 hash function FPGA design and the corresponding HMAC FPGA design is presented. Advanced optimization techniques have been deployed leading to a SHA-256 hashing core which performs more than 30% better, compared to the next better design. This improvement is achieved both in terms of throughput as well as in terms of throughput/area cost factor. It is the first reported SHA-256 hashing core that exceeds 11Gbps (after place and route in Xilinx Virtex 6 board).