Handbook of Applied Cryptography
Handbook of Applied Cryptography
A 12 Gbps DES Encryptor/Decryptor Core in an FPGA
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
High Performance Single-Chip FPGA Rijndael Algorithm Implementations
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Mapping the MD5 Hash Algorithm onto the NAPA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Pilchard — A Reconfigurable Computing Platform with Memory Slot Interface
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)
Proceedings of the conference on Design, automation and test in Europe - Volume 3
An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)
Proceedings of the 14th ACM Great Lakes symposium on VLSI
ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
Cost-efficient SHA hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Hardware Architecture of SHA-256 Algorithm for Trusted Mobile Computing
Information Security and Cryptology
Improving SHA-2 hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256
Microprocessors & Microsystems
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256
Computers and Electrical Engineering
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The design, implementation and system level performance of an efficient yet compact field programmable gate array (FPGA) based Secure Hash Algorithm 256 (SHA-256) processor is presented. On a Xilinx Virtex XCV300E-8 FPGA, the SHA-256 processor utilizes 1261 slices and has a throughput of 87 MB/s at 88 MHz. When measured on actual hardware operating at 66 MHz, it had a maximum measured system throughput of 53 MB/s.