FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256

Authors:
I. Algredo-Badillo;C. Feregrino-Uribe;R. Cumplido;M. Morales-Sandoval
Affiliations:
Computer Engineering, University of Istmo, Tehuantepec, Oaxaca 70760, Mexico;National Institute for Astrophysics, Optics and Electronics, Santa. Ma. Tonantzintla, Puebla 72840, Mexico;National Institute for Astrophysics, Optics and Electronics, Santa. Ma. Tonantzintla, Puebla 72840, Mexico;Polytechnic University of Victoria, Information Technology Department, Tamaulipas 87138, Mexico
Venue:
Microprocessors & Microsystems
Year:
2013

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Abstract

Hash function algorithms are widely used to provide security services of integrity and authentication, being SHA-2 the latest set of hash algorithms standardized by the US Federal Government. The main computation block in SHA-2 algorithms is governed by a loop with high data dependence for which several implementation strategies are explored in this work as well as designs efficiently mapped to hardware architectures. Four new different hardware architectures are proposed to improve the performance of SHA-256 algorithms, reducing the critical path by reordering some operations required at each iteration of the algorithm and computing some values in advance, as possible as data dependence allows. The proposed designs were implemented and validated in the FPGA Virtex-2 XC2VP-7. The achieved results show a significant improvement on the performance of the SHA-256 algorithm compared to similar previously proposed approaches, obtaining a throughput of 909Mbps and an improved efficiency of 0.713Mbps/slice.