An exploration of mechanisms for dynamic cryptographic instruction set extension
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256
Microprocessors & Microsystems
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This paper introduces the specialization of a NIOS2 processor targeting the computation of message authentication codes and integrity checks in constrained environments. Several hardware/software partitioning levels are considered, which vary from simple functions implemented as custom instructions to complete algorithms as peripherals. Our experimental results show that functions Sum, Sig, Ch, Maj implemented as custom instructions allows for SHA-256 and HMAC to be accelerated 1.38 and 1.36 times respectively, while keeping a small area footprint. If the entire SHA-256 algorithm is implemented as a peripheral, the hash computation is performed 11 times faster while decreasing the program size in 16%. Furthermore, the HMAC/SHA-256 peripheral accelerates the computation of a message authentication code 19 times with a 26% smaller program. These results allow for the specialization of the computational platform of constrained embedded systems to the processing requirements of cryptographic applications performing message authentication codes and integrity checks.