Handbook of Applied Cryptography
Handbook of Applied Cryptography
RIPEMD-160: A Strengthened Version of RIPEMD
Proceedings of the Third International Workshop on Fast Software Encryption
Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512
ISC '02 Proceedings of the 5th International Conference on Information Security
Implementation of the SHA-2 Hash Family Standard Using FPGAs
The Journal of Supercomputing
Efficient Hardware Architecture of SHA-256 Algorithm for Trusted Mobile Computing
Information Security and Cryptology
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256
Microprocessors & Microsystems
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256
Computers and Electrical Engineering
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We propose an improved implementation of the SHA-2 hash family, with minimal operator latency and reduced hardware requirements. We also propose a high frequency version at the cost of only two cycles of latency per message. Finally we present a multi-mode architecture able to perform either a SHA-384 or SHA-512 hash or to behave as two independent SHA-224 or SHA-256 operators. Such capability adds increased flexibility for applications ranging from a server running multiple streams to independent pseudorandom number generation. We also demonstrate that our architecture achieves a performance comparable to separate implementations while requiring much less hardware.