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Proceedings of the 15th international symposium on System Synthesis
An FPGA Based SHA-256 Processor
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512
ISC '02 Proceedings of the 5th International Conference on Information Security
Securing Mobile Appliances: New Challenges for the System Designer
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Implementation of the SHA-2 Hash Family Standard Using FPGAs
The Journal of Supercomputing
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ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
Optimisation of the SHA-2 Family of Hash Functions on FPGAs
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Multi-mode operator for SHA-2 hash functions
Journal of Systems Architecture: the EUROMICRO Journal
A Reconfigurable Implementation of the New Secure Hash Algorithm
ARES '07 Proceedings of the The Second International Conference on Availability, Reliability and Security
Improving SHA-2 hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
SPONGENT: a lightweight hash function
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Architectural support for hypervisor-secure virtualization
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Pushing the limits of SHA-3 hardware implementations to fit on RFID
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256
Computers and Electrical Engineering
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We present a compact SHA-256 hardware architecture suitable for the Trusted Mobile Platform (TMP), which requires low-area and low-power characteristics. The built-in hardware engine to compute a hash algorithm in TMP is one of the most important circuit blocks and contributes the performance of the whole platform because it is used as key primitives supporting platform integrity and command authentication. Unlike personal computers, mobile platform have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore, special architecture and design methods for a compact hash hardware module are required. Our SHA-256 hardware can compute 512-bit data block using 8,588 gates on a 0.25μm CMOS process. The highest operation frequency and throughput of the proposed architecture are 136MHz and 142Mbps, which satisfies processing requirement for the mobile application.