Pushing the limits of SHA-3 hardware implementations to fit on RFID

Authors:
Peter Pessl;Michael Hutter
Affiliations:
Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Graz, Austria;Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Graz, Austria
Venue:
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
Year:
2013

Citing 18
Cited 0

RFID Systems and Security and Privacy Implications

CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Networked RFID Systems and Lightweight Cryptography: Raising Barriers to Product Counterfeiting

Networked RFID Systems and Lightweight Cryptography: Raising Barriers to Product Counterfeiting
MAME: A Compression Function with Reduced Hardware Requirements

CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
SQUASH --- A New MAC with Provable Security Properties for Highly Constrained Devices Such as RFID Tags

Fast Software Encryption
Hash Functions and RFID Tags: Mind the Gap

CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Efficient Hardware Architecture of SHA-256 Algorithm for Trusted Mobile Computing

Information Security and Cryptology
Efficient hardware implementations of high throughput SHA-3 candidates keccak, luffa and blue midnight wish for single- and multi-message hashing

Proceedings of the 3rd international conference on Security of information and networks
QUARK: a lightweight hash

CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Developing a hardware evaluation method for SHA-3 candidates

CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs

CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
A lightweight implementation of Keccak hash function for radio-frequency identification applications

RFIDSec'10 Proceedings of the 6th international conference on Radio frequency identification: security and privacy issues
FPGA Implementations of the Round Two SHA-3 Candidates

FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
The PHOTON family of lightweight Hash functions

CRYPTO'11 Proceedings of the 31st annual conference on Advances in cryptology
SPONGENT: a lightweight hash function

CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Area-Efficient FPGA Implementations of the SHA-3 Finalists

RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
A case against currently used hash functions in RFID protocols

OTM'06 Proceedings of the 2006 international conference on On the Move to Meaningful Internet Systems: AWeSOMe, CAMS, COMINF, IS, KSinBIT, MIOS-CIAO, MONET - Volume Part I
Compact FPGA implementations of the five SHA-3 finalists

CARDIS'11 Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Lightweight implementations of SHA-3 candidates on FPGAs

INDOCRYPT'11 Proceedings of the 12th international conference on Cryptology in India

Quantified Score

Hi-index	0.00

Visualization

Abstract

There exists a broad range of RFID protocols in literature that propose hash functions as cryptographic primitives. Since keccak has been selected as the winner of the NIST SHA-3 competition in 2012, there is the question of how far we can push the limits of keccak to fulfill the stringent requirements of passive low-cost RFID. In this paper, we address this question by presenting a hardware implementation of keccak that aims for lowest power and lowest area. Our smallest (full-state) design requires only 2 927 GEs (for designs with external memory available) and 5 522 GEs (total size including memory). It has a power consumption of 12.5 μW at 1 MHz on a low leakage 130 nm CMOS process technology. As a result, we provide a design that needs 40% less resources than related work. Our design is even smaller than the smallest SHA-1 and SHA-2 implementations.