Preimages for Reduced SHA-0 and SHA-1
CRYPTO 2008 Proceedings of the 28th Annual conference on Cryptology: Advances in Cryptology
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication
Finding SHA-1 characteristics: general results and applications
ASIACRYPT'06 Proceedings of the 12th international conference on Theory and Application of Cryptology and Information Security
How to break MD5 and other hash functions
EUROCRYPT'05 Proceedings of the 24th annual international conference on Theory and Applications of Cryptographic Techniques
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Compact FPGA implementations of the five SHA-3 finalists
CARDIS'11 Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Towards green cryptography: a comparison of lightweight ciphers from the energy viewpoint
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Design and benchmarking of an ASIC with five SHA-3 finalist candidates
Microprocessors & Microsystems
Putting together what fits together: grÆstl
CARDIS'12 Proceedings of the 11th international conference on Smart Card Research and Advanced Applications
Study of ASIC technology impact factors on performance evaluation of SHA-3 candidates
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Fair and consistent hardware evaluation of fourteen round two SHA-3 candidates
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ASIC implementations of five SHA-3 finalists
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Pushing the limits of SHA-3 hardware implementations to fit on RFID
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
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The U.S. National Institute of Standards and Technology encouraged the publication of works that investigate and evaluate the performances of the second round SHA-3 candidates. Besides the hardware characterization of the 14 candidate algorithms, the main goal of this paper is the description of a reliable methodology to efficiently characterize and compare VLSI circuits of cryptographic primitives. We took the opportunity to apply it on the ongoing SHA-3 competition. To this end, we implemented several architectures in a 90 nm CMOS technology, targeting high- and moderate-speed constraints separately. Thanks to this analysis, we were able to present a complete benchmark of the achieved post-layout results of the circuits.