An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
An HMAC processor with integrated SHA-1 and MD5 algorithms
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Using Normal Bases for Compact Hardware Implementations of the AES S-Box
SCN '08 Proceedings of the 6th international conference on Security and Cryptography for Networks
Implementation of the AES-128 on virtex-5 FPGAs
AFRICACRYPT'08 Proceedings of the Cryptology in Africa 1st international conference on Progress in cryptology
Developing a hardware evaluation method for SHA-3 candidates
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
On FPGA-Based Implementations of the SHA-3 Candidate Grøstl
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
Pushing the limits: a very compact and a threshold implementation of AES
EUROCRYPT'11 Proceedings of the 30th Annual international conference on Theory and applications of cryptographic techniques: advances in cryptology
Area-Efficient FPGA Implementations of the SHA-3 Finalists
RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
Energy comparison of AES and SHA-1 for ubiquitous computing
EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
AES on FPGA from the fastest to the smallest
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Low power AES hardware architecture for radio frequency identification
IWSEC'06 Proceedings of the 1st international conference on Security
Compact FPGA implementations of the five SHA-3 finalists
CARDIS'11 Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
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We present GrÆStl, a combined hardware architecture for the Advanced Encryption Standard (AES) and Grøstl, one of the final round candidates of the SHA-3 hash competition. GrÆStl has been designed for low-resource devices implementing AES-128 (encryption and decryption) as well as Grøstl-256 (tweaked version). We applied several resource-sharing optimizations and based our design on an 8/16-bit datapath. As a feature, we aim for high flexibility by targeting both ASIC and FPGA platforms and do not include technology or platform-dependent components such as RAM macros, DSPs, or Block RAMs. Our ASIC implementation (fabricated in a 0.18μm CMOS process) needs only 16.5 kGEs and requires 742/1,025 clock cycles for encryption/decryption and 3,093 clock cycles for hashing one message block. On a Xilinx Spartan-3 FPGA, our design requires 956 logic slices and 302 logic slices on a Xilinx Virtex-6. Both stand-alone implementations of AES and Grøstl outperform existing FPGA solutions regarding low-area design by needing 79% and 50% less resources as compared to existing work. GrÆStl is the first combined AES and Grøstl implementation that has been fabricated as an ASIC.