Introduction to finite fields and their applications
Introduction to finite fields and their applications
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Security of a Wide Trail Design
INDOCRYPT '02 Proceedings of the Third International Conference on Cryptology: Progress in Cryptology
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
A 2 Gb/s balanced AES crypto-chip implementation
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A High Performance Sub-Pipelined Architecture for AES
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A configurable AES processor for enhanced security
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
IEEE Transactions on Computers
FPGA implementations of the ICEBERG block cipher
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
On the implementation of the advanced encryption standard on a public-key crypto-coprocessor
CARDIS'02 Proceedings of the 5th conference on Smart Card Research and Advanced Application Conference - Volume 5
An area optimized reconfigurable encryptor for AES-Rijndael
Proceedings of the conference on Design, automation and test in Europe
Area, delay, and power characteristics of standard-cell implementations of the AES S-Box
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
DPA-Resistance Without Routing Constraints?
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
AES Encryption Implementation and Analysis on Commodity Graphics Processing Units
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A Practical DPA Countermeasure with BDD Architecture
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Comparative Evaluation of Rank Correlation Based DPA on an AES Prototype Chip
ISC '08 Proceedings of the 11th international conference on Information Security
Using Normal Bases for Compact Hardware Implementations of the AES S-Box
SCN '08 Proceedings of the 6th international conference on Security and Cryptography for Networks
A New DPA Countermeasure Based on Permutation Tables
SCN '08 Proceedings of the 6th international conference on Security and Cryptography for Networks
Practical symmetric key cryptography on modern graphics hardware
SS'08 Proceedings of the 17th conference on Security symposium
Practical Attacks on Masked Hardware
CT-RSA '09 Proceedings of the The Cryptographers' Track at the RSA Conference 2009 on Topics in Cryptology
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Journal of Electronic Testing: Theory and Applications
A compact ASIC implementation of the advanced encryption standard with concurrent error detection
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
On the ability of AES S-boxes to secure against correlation power analysis
ISPEC'07 Proceedings of the 3rd international conference on Information security practice and experience
A very compact "Perfectly masked" S-box for AES
ACNS'08 Proceedings of the 6th international conference on Applied cryptography and network security
Single- and multi-core configurable AES architectures for flexible security
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the ACM SIGCOMM 2010 conference
BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation
Proceedings of the Conference on Design, Automation and Test in Europe
Design research of the DES against power analysis attacks based on FPGA
Microprocessors & Microsystems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FastCrypto: parallel AES pipelines extension for general-purpose processors
Neural, Parallel & Scientific Computations
Faster secure two-party computation using garbled circuits
SEC'11 Proceedings of the 20th USENIX conference on Security
Design of an ultra high speed AES processor for next generation IT security
Computers and Electrical Engineering
Threshold implementations against side-channel attacks and glitches
ICICS'06 Proceedings of the 8th international conference on Information and Communications Security
An instruction set extension for fast and memory-efficient AES implementation
CMS'05 Proceedings of the 9th IFIP TC-6 TC-11 international conference on Communications and Multimedia Security
A side-channel analysis resistant description of the AES s-box
FSE'05 Proceedings of the 12th international conference on Fast Software Encryption
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A systematic evaluation of compact hardware implementations for the rijndael s-box
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Side-channel leakage of masked CMOS gates
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Efficient AES implementations on ASICs and FPGAs
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Small size, low power, side channel-immune AES coprocessor: design and synthesis results
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Representations and rijndael descriptions
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Successfully attacking masked AES hardware implementations
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Secure AES hardware module for resource constrained devices
ESAS'04 Proceedings of the First European conference on Security in Ad-hoc and Sensor Networks
Area, delay, and power characteristics of standard-cell implementations of the AES s-box
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Low power AES hardware architecture for radio frequency identification
IWSEC'06 Proceedings of the 1st international conference on Security
Bitslice implementation of AES
CANS'06 Proceedings of the 5th international conference on Cryptology and Network Security
Side-Channel leakage across borders
CARDIS'10 Proceedings of the 9th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Application
An efficient masking scheme for AES software implementations
WISA'05 Proceedings of the 6th international conference on Information Security Applications
Putting together what fits together: grÆstl
CARDIS'12 Proceedings of the 11th international conference on Smart Card Research and Advanced Applications
Construction of optimum composite field architecture for compact high-throughput AES S-boxes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Masked dual-rail precharge logic encounters state-of-the-art power analysis methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Integration, the VLSI Journal
AES side-channel countermeasure using random tower field constructions
Designs, Codes and Cryptography
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This article presents a hardware implementation of the S-Boxes from the Advanced Encryption Standard (AES). The SBoxes substitute an 8-bit input for an 8-bit output and are based on arithmetic operations in the finite field GF(28). We show that a calculation of this function and its inverse can be done efficiently with combinational logic. This approach has advantages over a straight-forward implementation using read-only memories for table lookups. Most of the functionality is used for both encryption and decryption. The resulting circuit offers low transistor count, has low die-size, is convenient for pipelining, and can be realized easily within a semi-custom design methodology like a standard-cell design. Our standard cell implementation on a 0.6 碌m CMOS process requires an area of only 0.108 mm2 and has delay below 15 ns which equals a maximum clock frequency of 70 MHz. These results were achieved without applying any speed optimization techniques like pipelining.