Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Design of Rijndael
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
High Performance Single-Chip FPGA Rijndael Algorithm Implementations
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
A novel AES-256 implementation on FPGA using co-processor based architecture
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
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In this paper, an efficient sub-pipelined architecture for AES is proposed. It can do both encryption and decryption with well evenly divided three-stage pipeline. The threestage pipelined key expansion module generates the corresponding subkeys concurrently for encryption or decryption. The design can operate in CBCk mode and process three blocks of data simultaneously. The proposed architecture is simulated in Verilog HDL and implemented using Xilinx Virtex II FPGA device. The comparison indicates that our design has a relatively low area and high throughput up to 1.57Gbits/s.