A novel AES-256 implementation on FPGA using co-processor based architecture

  • Authors:
  • Suman Sau;Rourab Paul;Tanmay Biswas;Amlan Chakrabarti

  • Affiliations:
  • University Of Calcutta Kolkata, India;University Of Calcutta Kolkata, India;Technology University Of Calcutta Kolkata, India;University of Calcutta Kolkata, India

  • Venue:
  • Proceedings of the International Conference on Advances in Computing, Communications and Informatics
  • Year:
  • 2012

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Abstract

Efficient hardware architecture for cryptographic algorithms are of utmost need for implementing secured data communication in embedded applications. The hardware implementation of the algorithms though provides less flexibility, but are faster and requires less resource as compared to the software implementation, and hence ideally suited for target specific embedded systems. Though, there exist quite a few research works that propose hardware design for implementing cryptographic algorithm on various hardware platforms like application specific integrated circuit (ASIC), field programmable gate array (FPGA) and micro-controllers, still there lies the need of better hardware design in terms of larger key values, higher throughput and less resource utilization.