A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Real 802.11 Security: Wi-Fi Protected Access and 802.11i
Real 802.11 Security: Wi-Fi Protected Access and 802.11i
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard
Computers and Electrical Engineering
An efficient design of security accelerator for IEEE 802.15.4 wireless sensor networks
CCNC'10 Proceedings of the 7th IEEE conference on Consumer communications and networking conference
A novel AES-256 implementation on FPGA using co-processor based architecture
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
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For high data rate, new mechanisms such as Block Ack and frame aggregation are currently being discussed in IEEE 802.11e and IEEE 802.11n, respectively. These mechanisms need a short response time in each MPDU processing. In this paper, we propose an efficient design of CCMP for IEEE 802.11i to support these new MAC mechanisms. The proposed design adopts the mode toggling approach, in which MIC calculation and data encryption are sequentially performed for each 128 bits of the packet in only one AESCCM core. In our design, the response time is reduced to a short constant period, which takes only 44 clock cycles. In addition, we can reduce hardware complexity and power consumption, because our design uses one AES-CCM core and obtains the reasonable data throughput and response time at even low clock frequency. We have implemented the proposed design, which is targeted to Altera Stratix FPGA device. As a result of the experiments, the CCMP features 285 Mbps data throughput and 0.88 μs . response time at 50 MHz frequency.