An FPGA implementation and performance evaluation of the Serpent block cipher
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
An Optimized S-Box Circuit Architecture for Low Power AES Design
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
MAC security and security overhead analysis in the IEEE 802.15.4 wireless sensor networks
EURASIP Journal on Wireless Communications and Networking
An FPGA implementation of CCM mode using AES
ICISC'05 Proceedings of the 8th international conference on Information Security and Cryptology
An efficient design of CCMP for robust security network
ICISC'05 Proceedings of the 8th international conference on Information Security and Cryptology
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In this paper, we provide a low cost AES core for ZigBee devices which accelerates the computation of AES algorithms. Also, by embedding the AES core, we present an efficient architecture of security accelerator satisfying the IEEE 802.15.4 specifications. In our experiments, we observed that the AES core and the security accelerator use fewer logic gates and consume lower power than other architectures based on blockwide and folded ones.