ISC '01 Proceedings of the 4th International Conference on Information Security
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
Reconfigurable hardware solutions for the digital rights management of digital cinema
Proceedings of the 4th ACM workshop on Digital rights management
An object-oriented cryptosystem based on two-level reconfigurable computing architecture
Journal of Systems and Software
Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications
Transactions on Data Privacy
VECPAR'06 Proceedings of the 7th international conference on High performance computing for computational science
Implementation of the AES-128 on virtex-5 FPGAs
AFRICACRYPT'08 Proceedings of the Cryptology in Africa 1st international conference on Progress in cryptology
An efficient design of security accelerator for IEEE 802.15.4 wireless sensor networks
CCNC'10 Proceedings of the 7th IEEE conference on Consumer communications and networking conference
A high-speed and area efficient hardware implementation of AES-128 encryption standard
MIV'05 Proceedings of the 5th WSEAS international conference on Multimedia, internet & video technologies
Configurable computing for high-security/high-performance ambient systems
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Reprogrammable devices such as Field Programmable Gate Arrays (FPGA's) are highly attractive options for hardware implementations of encryption algorithms and this report investigates a methodology to efficiently implement block ciphers in CLB-based FPGA's. Our methodology is applied to the new Advanced Encryption Standard RIJNDAEL and the resulting designs offer better performances than previously published in literature. We propose designs that unroll the 10 AES rounds and pipeline them in order to optimize the frequency and throughput results. In addition, we implemented solutions that allow to change the plaintext and the key on a cycle-by-cycle basis with no dead cycles. Another strong focus is placed on low area circuits and we propose sequential designs with very low area requirements. Finally we demonstrate that RAM-based implementations implies different constraints but our methodology still holds.