A versatile pipelined hardware implementation for encryption and decryption using advanced encryption standard

Authors:
Nadia Nedjah;Luiza de Macedo Mourelle
Affiliations:
Department of Electronics Engineering and Telecommunications, Faculty of Engineering, State University of Rio de Janeiro, Brazil;Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Brazil
Venue:
VECPAR'06 Proceedings of the 7th international conference on High performance computing for computational science
Year:
2006

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Abstract

The Advanced Encryption System - AES is now used in almost all network-based applications to ensure security. In this paper, we propose a very efficient pipelined hardware implementation of AES- 128. The design is versatile as it allows both encryption and decryption. The core computation of AES, which is performed on data blocks of 128 bits, is iterated for several rounds, depending on the key size. The security strength of AES has been proven proportional to the number of rounds applied. we show that if the required number of rounds must increase to defeat attackers, the proposed implementation stays efficient.