AES Implementation on FPGA: Time - Flexibility Tradeoff

Authors:
Anna Labbé;Annie Pérez
Affiliations:
-;-
Venue:
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Year:
2002

Citing 5
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Abstract

This paper presents some FPGA-based implementations of the private key Advanced Encryption Standard (AES) cryptography algorithm. The technological fixed target is one V1000BG560 Xilinx Virtex FPGA. A basic architecture is presented first for a 256-bit Cipher Key and a 256-bit Block configuration. Partially pipelined structures were also implemented and perform a throughput rate proportional to the pipeline degree. These improved architectures can ensure high speed encryption by processing several Blocks of the plaintext concurrently. In return they need more logic resources. The resources being limited to the Virtex device ones, the highest speed implementations will loose flexibility as for the choice of the number of bits coding the Cipher Key or the Blocks. Different implementation results illustrating this time - flexibility tradeoff are presented and commented.