Virtual private networks: making the right connection
Virtual private networks: making the right connection
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
AES Implementation on FPGA: Time - Flexibility Tradeoff
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
ISC '01 Proceedings of the 4th International Conference on Information Security
Configuration compression for FPGA-based embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we study and compare the performance of FPGA-based implementations of the five final AES candidates (MARS, RC6, Rijndael, Serpent, and Twofish). Our goal is to evaluate the suitability of the aforementioned algorithms for FPGA-based implementations. Among the various time-space implementation tradeoffs, we focused primarily on time performance. The time performance metrics are throughput and key-setup latency. Throughput corresponds to the amount of data processed per time unit while the key-setup latency time is the minimum time required to commence encryption after providing the input key. Time performance and area requirement results are provided for all the final AES candidates. To the best of our knowledge, we are not aware of any published results that include key-setup latency results. Our results suggest that Rijndael and Serpent favor FPGA implementations the most since their algorithmic characteristics match extremely well with the hardware characteristics of FPGAs.