A Comparative Study of Performance of AES Final Candidates Using FPGAs
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
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FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Architectures and VLSI Implementations of the AES-Proposal Rijndael
IEEE Transactions on Computers
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FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
ISC '01 Proceedings of the 4th International Conference on Information Security
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ISC '02 Proceedings of the 5th International Conference on Information Security
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Proceedings of the 14th ACM Great Lakes symposium on VLSI
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ACM Transactions on Embedded Computing Systems (TECS)
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IEEE Transactions on Parallel and Distributed Systems
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
IEEE Transactions on Computers
FPGA implementations of the ICEBERG block cipher
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
FPGA implementation(s) of a scalable encryption algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
Microelectronics Journal
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International Journal of Parallel Programming
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Computers and Electrical Engineering
DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for AES on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
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NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
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ICIC'09 Proceedings of the 5th international conference on Emerging intelligent computing technology and applications
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International Journal of Critical Computer-Based Systems
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
FastCrypto: parallel AES pipelines extension for general-purpose processors
Neural, Parallel & Scientific Computations
Design of an ultra high speed AES processor for next generation IT security
Computers and Electrical Engineering
A systematic evaluation of compact hardware implementations for the rijndael s-box
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Configurable computing for high-security/high-performance ambient systems
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Design and implementation of an FPGA-Based 1.452-gbps non-pipelined AES architecture
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part III
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The results of fast implementations of all five AES final candidates using Virtex Xilinx Field Programmable Gate Arrays are presented and analyzed. Performance of several alternative hardware architectures is discussed and compared. One architecture optimum from the point of view of the throughput to area ratio is selected for each of the two major types of block cipher modes. For feedback cipher modes, all AES candidates have been implemented using the basic iterative architecture, and achieved speeds ranging from 61 Mbit/s for Mars to 431 Mbit/s for Serpent. For non-feedback cipher modes, four AES candidates have been implemented using a high-throughput architecture with pipelining inside and outside of cipher rounds, and achieved speeds ranging from 12.2 Gbit/s for Rijndael to 16.8 Gbit/s for Serpent. A new methodology for a fair comparison of the hardware performance of secret-key block ciphers has been developed and contrasted with methodology used by the NSA team.