64-bit Block ciphers: hardware implementations and comparison analysis

Authors:
P. Kitsos;N. Sklavos;M. D. Galanis;O. Koufopavlou
Affiliations:
VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, 26500 Rio, Patras, Greece;VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, 26500 Rio, Patras, Greece;VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, 26500 Rio, Patras, Greece;VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, 26500 Rio, Patras, Greece
Venue:
Computers and Electrical Engineering
Year:
2004

Citing 8
Cited 3

A proposal for a new block encryption standard

EUROCRYPT '90 Proceedings of the workshop on the theory and application of cryptographic techniques on Advances in cryptology
UNIX password security—ten years later

CRYPTO '89 Proceedings on Advances in cryptology
Universal strong encryption FPGA core implementation

Proceedings of the conference on Design, automation and test in Europe
Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays

CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board

ISC '01 Proceedings of the 4th International Conference on Information Security
Configurable hardware implementation of triple-DES encryption algorithm for wireless local area network

ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02

An efficient cryptosystem Delta for stream cipher applications

Computers and Electrical Engineering
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration

Microelectronics Journal
Full custom low-power/high performance DDP-based Cobra-H64 cipher

Computers and Electrical Engineering

Quantified Score

Hi-index	0.00

Visualization

Abstract

A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are under consideration from the ISO/IEC 18033-3 standard in order to provide an international encryption standard for the 64-bit block ciphers. Two basic architectures are implemented for each cipher. For the non-feedback cipher modes, the pipelined technique between the rounds is used, and the achieved throughput ranges from 3.0Gbps for IDEA to 6.9Gbps for Triple-DES. For feedback ciphers modes, the basic iterative architecture is considered and the achieved throughput ranges from 115Mbps for Triple-DES to 462Mbps for KHAZAD. The throughput, throughput per slice, latency, and area requirement results are provided for all the ciphers implementations. Our study is an effort to determine the most suitable algorithm for hardware implementation with FPGA devices.