Reconfigurable hardware solutions for the digital rights management of digital cinema
Proceedings of the 4th ACM workshop on Digital rights management
An object-oriented cryptosystem based on two-level reconfigurable computing architecture
Journal of Systems and Software
Breaking Legacy Banking Standards with Special-Purpose Hardware
Financial Cryptography and Data Security
64-bit Block ciphers: hardware implementations and comparison analysis
Computers and Electrical Engineering
BRAM-LUT tradeoff on a polymorphic DES design
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Sparse Boolean equations and circuit lattices
Designs, Codes and Cryptography
Breaking ciphers with COPACOBANA –a cost-optimized parallel code breaker
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Hi-index | 0.00 |
We propose a new mathematical DES description that allows optimized implementations. It also provides the best DES and triple-DES FPGA implementations known in term of ratio throughput/area, where area means the number of FPGA slices used. First, we get a less resource consuming unrolled DES implementation that works at data rates of 21.3 Gbps (333 MHz), using VIRTEX II technology. In this design, the plaintext, the key and the mode (encryption/decrytion) can be changed on a cycle-by-cycle basis with no dead cycles. In addition, we also propose sequential DES and triple-DES designs that are currently the most efficient ones in term of resources used as well as in term of throughput. Based on our DES and triple-DES results, we also set up conclusions for optimized FPGA design choices and possible improvement of cipher implementations with a modified structure description.