Reconfigurable hardware solutions for the digital rights management of digital cinema

Authors:
G. Rouvroy;F.-X. Standaert;F. Lefèbvre;J.-J. Quisquater;B. Macq;J.-D. Legat
Affiliations:
Laboratoire de Microélectronique, Louvain-la-Neuve, Belgium;Laboratoire de Microélectronique, Louvain-la-Neuve, Belgium;Laboratoire de Télécommunications et Télédection, Louvain-la-Neuve, Belgium;Laboratoire de Microélectronique, Louvain-la-Neuve, Belgium;Laboratoire de Télécommunications et Télédection, Louvain-la-Neuve, Belgium;Laboratoire de Microélectronique, Louvain-la-Neuve, Belgium
Venue:
Proceedings of the 4th ACM workshop on Digital rights management
Year:
2004

Citing 7
Cited 0

Watermarking algorithm based on a human visual model

Signal Processing
JPEG 2000: Image Compression Fundamentals, Standards and Practice

JPEG 2000: Image Compression Fundamentals, Standards and Practice
A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis

IEEE Transactions on Computers
Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications

ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
A high-performance JPEG2000 architecture

IEEE Transactions on Circuits and Systems for Video Technology

Quantified Score

Hi-index	0.02

Visualization

Abstract

This paper presents a hardware implementation of a decoder for Digital Cinema images. This decoder enables us to deal with image size of 2K with 24 frames per second and 36 bits per pixels. It is the first implementation known nowadays that perfectly fits in one single Virtex-II® FPGA and includes AES decryption, JPEG 2000 decompression and fingerprinting blocks. This hardware offers therefore high-quality image processing as well as robust security.