Reconfigurable hardware solutions for the digital rights management of digital cinema
Proceedings of the 4th ACM workshop on Digital rights management
An improved bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A scalable embedded JPEG 2000 architecture
Journal of Systems Architecture: the EUROMICRO Journal
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Design and analysis of system on a chip encoder for JPEG2000
IEEE Transactions on Circuits and Systems for Video Technology
Variable-bin-rate CABAC engine for H.264/AVC high definition real-time decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable lossless high definition image coding on multicore platforms
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Efficient VLSI architecture for bit plane encoder of JPEG 2000
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
Multiresolution HVS and statistically based image coding scheme
Multimedia Tools and Applications
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000
Integration, the VLSI Journal
ICIAP'05 Proceedings of the 13th international conference on Image Analysis and Processing
A scalable embedded JPEG2000 architecture
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Two-Symbol FPGA Architecture for Fast Arithmetic Encoding in JPEG 2000
Journal of Signal Processing Systems
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JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination. These features are possible due to adaptation of the discrete wavelet transform, intra-subband bit-plane coding, and binary arithmetic coding in the standard. We propose a system-level architecture capable of encoding and decoding the JPEG2000 core algorithm that has been defined in Part I of the standard. The key components include dedicated architectures for wavelet, bit plane, and arithmetic coders and memory interfacing between the coders. The system architecture has been implemented in VHDL and its performance evaluated for a set of images. The estimated area of the architecture, in 0.18-μ technology, is 3-mm square and the estimated frequency of operation is 200 MHz.