An improved bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000

Authors:
Yanju Han;Chao Xu;Yizhen Zhang
Affiliations:
Peking University, Beijing, China;Peking University, Beijing, China;Peking University, Beijing, China
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

Citing 2
Cited 0

A high-performance JPEG2000 architecture

IEEE Transactions on Circuits and Systems for Video Technology
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000

IEEE Transactions on Circuits and Systems for Video Technology

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Abstract

Embedded block coding with optimized truncation (EBCOT) is a critical part in JPEG2000 systems. There are bit-plane and pass dual parallel methods that can speed up the encoding, but the acceleration is always companied with the complication of the circuit structure and the increase of the circuit resources. In this paper, we present an improved bit-plane and pass dual parallel architecture (IBPDP), which not only achieves a high encoding speed but also reduces the logic circuit requirement and the coding delay. Experimental results show that about 45% of the logic circuit is reduced and that the average fall of the delay per code-block is 10% compared with BPDP.