A Theory for Multiresolution Signal Decomposition: The Wavelet Representation
IEEE Transactions on Pattern Analysis and Machine Intelligence
JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures
JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures
A Survey on Lifting-based Discrete Wavelet Transform Architectures
Journal of VLSI Signal Processing Systems
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
Efficient architectures for 1-D and 2-D lifting-based wavelet transforms
IEEE Transactions on Signal Processing
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
IEEE Transactions on Signal Processing
High performance scalable image compression with EBCOT
IEEE Transactions on Image Processing
A high-performance JPEG2000 architecture
IEEE Transactions on Circuits and Systems for Video Technology
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
Memory efficient progressive rate-distortion algorithm for JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
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In this paper, we presented VLSI algorithms and architectures for JPEG2000. JPEG2000 is the new standard for image compression. We briefly described the core algorithms for JPEG2000 standard and its several features desirable in many interactive multimedia applications. The core compression algorithm has three major components - discrete wavelet transform (DWT), fractional bit plane coding (BPC), and context adaptive binary arithmetic coding. DWT and BPC are very computationally, as well as memory expensive operations. As a result, special purpose VLSI implementations of these algorithms are desirable for many devices to compress large size images in real time. Traditionally, the DWT is realized by convolution based finite impulse response (FIR) filtering techniques. However, Lifting based implementation of DWT is found to be computationally efficient and suitable for VLSI implementations. The basic principle behind the lifting based scheme is to decompose the finite impulse response filters in wavelet transform into a finite sequence of simple filtering steps. Lifting based DWT implementation have been recommended in JPEG2000 standard. Consequently, this has become an area of active research and several architectures have been proposed in recent years. In this paper, we reviewed some of the key lifting architectures suitable for VLSI implementation. The embedded block coding with optimized truncation (EBCOT) algorithm has been adopted for computation of BPC in JPEG2000. This algorithm is complex and inefficient to implement in a general purpose machine. We have described a special purpose architecture suitable for VLSI implementation of EBCOT algorithm. We also reviewed some elegant architectures in the literature which exploit the underlying data and computational parallelism inherent in the EBCOT algorithms. We also presented a top-level systems architecture for VLSI implementation of the JPEG2000 standard.