A Survey on Lifting-based Discrete Wavelet Transform Architectures
Journal of VLSI Signal Processing Systems
Analysis of Lifting and B-Spline DWT Implementations for Implantable Neuroprosthetics
Journal of Signal Processing Systems
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Expert Systems with Applications: An International Journal
A Block-Based Architecture for Lifting Scheme Discrete Wavelet Transform
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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Applied Soft Computing
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An efficient folded architecture for lifting-based discrete wavelet transform
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VLSI architectures for lifting based DWT: a detailed survey
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
High speed VLSI implementation of lifting based DWT
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
Algorithms and architectures for 2D discrete wavelet transform
The Journal of Supercomputing
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The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based DWTs, namely, one-dimensional (1-D) and two-dimensional (2-D) versions of what we call recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a five-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The recursive and dual scan architectures can be readily extended to the 2-D case. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array. The 2-D dual scan architecture processes the column and row transforms simultaneously, and the memory buffer size is comparable to existing architectures.