Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Deeply Parallel Architecture for Lifting-Based 2D DWT in JPEG2000
CIT '06 Proceedings of the Sixth IEEE International Conference on Computer and Information Technology
Efficient architectures for 1-D and 2-D lifting-based wavelet transforms
IEEE Transactions on Signal Processing
Line-based, reduced memory, wavelet image compression
IEEE Transactions on Image Processing
Evaluation of design alternatives for the 2-D-discrete wavelet transform
IEEE Transactions on Circuits and Systems for Video Technology
| Hi-index | 0.00 |
A novel two-dimensional discrete wavelet transform (2-DDWT) parallel architecture for higher throughput and lower energy consumption is proposed. The proposed architecture fully exploits full-page burst accesses of DRAM and minimizes the number of DRAM activate and precharge operations. Simulation results revealed that the architecture reduces the number of clock cycles for DRAM memory accesses as well as the DRAM power consumption with moderate cost of internal memory. Evaluation of the VLSI implementation of the architecture showed that the throughput of wavelet filtering was increased by parallelizing row filtering with a minimum area cost, thereby enabling DRAM full-page burst accesses to be exploited.