Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A 2-DDWT parallel architecture fully exploiting DRAM burst accesses
SPPRA '08 Proceedings of the Fifth IASTED International Conference on Signal Processing, Pattern Recognition and Applications
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As an indispensable and time-consuming component in JPEG2000, lifting-based 2D DWT is often implemented with a dedicated hardware in systems which require realtime processing. However, most of the proposed architectures for 2D DWT failed to achieve high performance since they didn't fully exploit the potential parallelisms within the algorithm. In this paper, we propose a deeply parallel architecture which can exploit all the parallelisms in 2D DWT algorithm. The architecture includes two row processors and two column processors which we call it a 2脳2 array. These processors are organized as interleaving dual pipelines being capable to produce two results every cycle. The architecture takes N^2/4+N/2+1 time units to finish a N脳N 2D DWT while requires only 3N+2 buffers to store the intermediate data. And also, we develop our design in Verilog HDL and synthesize it for Altera Stratix II FPGA family. The estimated frequency of operation is 145.54MHz.