Multiresolution Signal Decomposition: Transforms, Subbands, and Wavelets
Multiresolution Signal Decomposition: Transforms, Subbands, and Wavelets
A Survey on Lifting-based Discrete Wavelet Transform Architectures
Journal of VLSI Signal Processing Systems
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
Efficient architectures for 1-D and 2-D lifting-based wavelet transforms
IEEE Transactions on Signal Processing
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
IEEE Transactions on Signal Processing
Low-power and high-speed VLSI architecture for lifting-based forward and inverse wavelet transform
IEEE Transactions on Consumer Electronics
Lifting factorization-based discrete wavelet transform architecture design
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Area- and power-efficient design of Daubechies wavelet transforms using folded AIQ mapping
IEEE Transactions on Circuits and Systems II: Express Briefs
A pipeline VLSI architecture for high-speed computation of the 1-D discrete wavelet transform
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Computer Networks: The International Journal of Computer and Telecommunications Networking
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In this brief an efficient folded architecture (EFA) for lifting-based discrete wavelet transform (DWT) is presented. The proposed EFA is based on a novel form of the lifting scheme that is given in this brief. Due to this form, the conventional serial operations of the lifting data flow can be optimized into parallel ones by employing parallel and pipeline techniques. The corresponding optimized architecture (OA) has short critical path latency and is repeatable. Further, utilizing this repeatability, the EFA is derived from the OA by employing the fold technique. For the proposed EFA, hardware utilization achieves 100%, and the number of required registers is reduced. Additionally, the shift-add operation is adopted to optimize the multiplication; thus, the proposed architecture is more suitable for hardware implementation. Performance comparisons and field-programmable gate array (FPGA) implementation results indicate that the proposed EFA possesses better performances in critical path latency, hardware cost, and control complexity.