MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
An efficient folded architecture for lifting-based discrete wavelet transform
IEEE Transactions on Circuits and Systems II: Express Briefs
ACM Transactions on Embedded Computing Systems (TECS)
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
Journal of Signal Processing Systems
Journal of Signal Processing Systems
Reconfigurable architecture for VLSI 9/7-5/3 wavelet filter
IMCAS'10 Proceedings of the 9th WSEAS international conference on Instrumentation, measurement, circuits and systems
Reconfigurable architecture for VLSI 9/7-5/3 wavelet filter
WSEAS Transactions on Circuits and Systems
Area- and power-efficient design of Daubechies wavelet transforms using folded AIQ mapping
IEEE Transactions on Circuits and Systems II: Express Briefs
CSS'11 Proceedings of the 5th WSEAS international conference on Circuits, systems and signals
VLSI architectures for lifting based DWT: a detailed survey
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
High speed VLSI implementation of lifting based DWT
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
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In this paper, we propose a high-performance and memory-efficient pipeline architecture which performs the one-level two-dimensional (2-D) discrete wavelet transform (DWT) in the 5/3 and 9/7 filters. In general, the internal memory size of 2-D architecture highly depends on the pipeline registers of one-dimensional (1-D) DWT. Based on the lifting-based DWT algorithm, the primitive data path is modified and an efficient pipeline architecture is derived to shorten the data path. Accordingly, under the same arithmetic resources, the 1-D DWT pipeline architecture can operate at a higher processing speed (up to 200 MHz in 0.25-μm technology) than other pipelined architectures with direct implementation. The proposed 2-D DWT architecture is composed of two 1-D processors (column and row processors). Based on the modified algorithm, the row processor can partially execute each row-wise transform with only two column-processed data. Thus, the pipeline registers of 1-D architecture do not fully turn into the internal memory of 2-D DWT. For an N×M image, only 3.5N internal memory is required for the 5/3 filter, and 5.5N is required for the 9/7 filter to perform the one-level 2-D DWT decomposition with the critical path of one multiplier delay (i.e., N and M indicate the height and width of an image). The pipeline data path is regular and practicable. Finally, the proposed architecture implements the 5/3 and 9/7 filters by cascading the three key components.