Memory-efficient and high-speed line-based architecture for 2-D discrete wavelet transform with lifting scheme

  • Authors:
  • Tze-Yun Sung

  • Affiliations:
  • Department of Microelectronics Engineering, Chung Hua University, Hsinchu, Taiwan

  • Venue:
  • MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
  • Year:
  • 2007

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Abstract

In this paper, a high-efficient lined-based architecture for the 9/7 discrete wavelet transform (DWT) based on lifting scheme is proposed. The proposed parallel and pipelined architecture consists of a horizontal filter (HF) and a vertical filter (VF). The critical path of the proposed architecture is reduced. Filter coefficients of the biorthogonal 9/7 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware. In the proposed architecture, all multiplications are performed using less shifts and additions. The proposed architecture is 100% hardware utilization and ultra low-power. The architecture has regular structure, simple control flow, high throughput and high scalability. Thus, it is very suitable for new-generation image compression systems, such as JPEG-2000.