A Theory for Multiresolution Signal Decomposition: The Wavelet Representation
IEEE Transactions on Pattern Analysis and Machine Intelligence
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations
Journal of VLSI Signal Processing Systems
VLSI Implementation for One-Dimensional Multilevel Lifting-Based Wavelet Transform
IEEE Transactions on Computers
An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A Survey on Lifting-based Discrete Wavelet Transform Architectures
Journal of VLSI Signal Processing Systems
SSIP'07 Proceedings of the 7th WSEAS International Conference on Signal, Speech and Image Processing
IEEE Transactions on Computers
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
Efficient architectures for 1-D and 2-D lifting-based wavelet transforms
IEEE Transactions on Signal Processing
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
IEEE Transactions on Signal Processing
High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform
IEEE Transactions on Signal Processing
VLSI architectures for discrete wavelet transforms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient architecture for two-dimensional discrete wavelet transform
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
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Efficient line based hardware architecture for the lifting based discrete wavelet of an image is proposed in this work. Lifting Scheme reduces the number of operations execution steps to almost one-half of those needed with a conventional convolution approach. Performance comparison of simulation results for lifting DWT using MATLAB and VHDL is done to verify the proper functionality of the developed module. The comparison of direct mapped and folded VLSI architectures for lifting schemes is presented in terms of speed and hardware requirements. The whole architecture is being optimized to achieve better speed up and higher hardware utilization by using a single clock for predict and update operation. The proposed architecture is implemented in Xilinx Spartan 3E FPGA. The data flow of the proposed architecture is regular, simple, control complexity and achieves 100% hardware utilization. The entire system runs at faster rate and reaches a speed performance suitable for real time stand-alone image/video applications.