VLSID '03 Proceedings of the 16th International Conference on VLSI Design
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization
Journal of VLSI Signal Processing Systems
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
Efficient architectures for 1-D and 2-D lifting-based wavelet transforms
IEEE Transactions on Signal Processing
An efficient architecture for two-dimensional discrete wavelet transform
IEEE Transactions on Circuits and Systems for Video Technology
Subband weighting with pixel connectivity for 3-D wavelet coding
IEEE Transactions on Image Processing
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Two-dimensional discrete wavelet transform (DWT) for processing image is conventionally designed by line-based architectures, which are simple and have low complexity. However, they suffer from two main shortcomings – the memory required for storing intermediate data and the long latency of computing wavelet coefficients. This work presents a new block-based architecture for computing lifting-based 2-D DWT coefficients. This architecture yields a significantly lower buffer size. Additionally, the latency is reduced from N2 down to 3N as compared to the line-based architectures. The proposed architecture supports the JPEG2000 default filters and has been realized in ARM-based ALTERA EPXA10 Development Board at a frequency of 44.33 MHz.