JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures
JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures
A high-performance JPEG2000 architecture
IEEE Transactions on Circuits and Systems for Video Technology
Parallel embedded block coding architecture for JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory
IEEE Transactions on Circuits and Systems for Video Technology
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This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18 μm process. The core area is 4.7 × 4.7 mm2 and the frequency is 160 MHz. A system including the codec enables image transmission of PC desktop with 8 ms delay.