IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Multimode embedded compression codec engine for power-aware video coding system
IEEE Transactions on Circuits and Systems for Video Technology
Scalable lossless high definition image coding on multicore platforms
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
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A 124 MSamples/s JPEG 2000 codec is implemented on a 20.1 mm2 die with 0.18 mum CMOS technology dissipating 385 mW at 1.8 V and 42 MHz. This chip is capable of processing 1920times1080 HD video at 30 fps. For previous works, the tile-level pipeline scheduling is used between the discrete wavelet transform (DWT) and embedded block coding (EBC). For a tile with size 256times256, it costs 175 kB on-chip SRAM for the architectures using on-chip tile memory or costs 310 MB/s SDRAM bandwidth for the architectures using off-chip tile memory. In this design, a level-switched scheduling is developed to eliminate tile memory and the DWT and the EBC are pipelined at pixel-level. This scheduling eliminates 175 kB on-chip SRAM and 310 MB/s off-chip SDRAM bandwidth. The level-switched DWT (LS-DWT) and the code-block switched EBC (CS-EBC) are developed to enable this scheduling. The codec functions are realized on an unified hardware, and hardware sharing between encoder and decoder reduces silicon area by 40%