JPEG2000: the upcoming still image compression standard
Pattern Recognition Letters
An overview of the basic principles of the Q-Coder adaptive binary arithmetic coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Dual Symbol Processing for MQ Arithmetic Coder in JPEG2000
CISP '08 Proceedings of the 2008 Congress on Image and Signal Processing, Vol. 1 - Volume 01
Design and analysis of system on a chip encoder for JPEG2000
IEEE Transactions on Circuits and Systems for Video Technology
A high performance MQ encoder architecture in JPEG2000
Integration, the VLSI Journal
Efficient VLSI architecture for bit plane encoder of JPEG 2000
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
High performance scalable image compression with EBCOT
IEEE Transactions on Image Processing
A high-performance JPEG2000 architecture
IEEE Transactions on Circuits and Systems for Video Technology
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
Parallel embedded block coding architecture for JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
Realizing Low-Cost High-Throughput General-Purpose Block Encoder for JPEG2000
IEEE Transactions on Circuits and Systems for Video Technology
VLSI Design of a High-Speed and Area-Efficient JPEG2000 Encoder
IEEE Transactions on Circuits and Systems for Video Technology
Performance Analysis and Architecture Design for Parallel EBCOT Encoder of JPEG2000
IEEE Transactions on Circuits and Systems for Video Technology
An Efficient Architecture for 3-D Discrete Wavelet Transform
IEEE Transactions on Circuits and Systems for Video Technology
An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
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The embedded block coding with optimized truncation (EBCOT) algorithm is the heart of the JPEG 2000 image compression system. The MQ coder used in this algorithm restricts throughput of the EBCOT because there is very high correlation among all procedures to be performed in it. To overcome this obstacle, a high throughput MQ coder architecture is presented in this paper. To accomplish this, we have studied the number of rotations performed and the rate of byte emission in an image. This study reveals that in an image, on an average 75.03% and 22.72% of time one and two shifts occur, respectively. Similarly, about 5.5% of time two bytes are emitted concurrently. Based on these facts, a new MQ coder architecture is proposed which is capable of consuming one symbol per clock cycle. The throughput of this coder is improved by operating the renormalization and byte out stages concurrently. To reduce the hardware cost, synchronous shifters are used instead of hard shifters. The proposed architecture is implemented on Stratix FPGA and is capable of operating at 145.9MHz. Memory requirement of the proposed architecture is reduced by a minimum of 66% compared to those of the other existing architectures. Relative figure of merit is computed to compare the overall efficiency of all architectures which show that the proposed architecture provides good balance between the throughput and hardware cost.