A high performance MQ encoder architecture in JPEG2000

Authors:
Kai Liu;Yu Zhou;Yun Song Li;Jian Feng Ma
Affiliations:
School of Computer Science and Technology, Xidian University, Xi'an 710071, China;National Key Laboratory of Integrated Service Networks, Xidian University, Xi'an 710071, China;National Key Laboratory of Integrated Service Networks, Xidian University, Xi'an 710071, China;School of Computer Science and Technology, Xidian University, Xi'an 710071, China
Venue:
Integration, the VLSI Journal
Year:
2010

Citing 2
Cited 2

An overview of the basic principles of the Q-Coder adaptive binary arithmetic coder

IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000

IEEE Transactions on Circuits and Systems for Video Technology

VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000

Integration, the VLSI Journal
Low GPU occupancy approach to fast arithmetic coding in JPEG2000

MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, a novel architecture for an MQ arithmetic coder with high throughput is proposed. The architecture can process two symbols in parallel. The main characteristics are eight process elements for the prediction of probability interval A, the combination of calculation units for the code register C with the Byteout&Flush procedure, and the use of a dedicated probability estimation table to decrease the internal memory. From FPGA synthesis results, the architecture's throughput can reach 96.60M context symbols per second with an internal memory size of 1509 bits, which is comparable to that of other architectures and suitable for chip implementation.