Approximate counting: a detailed analysis
BIT - Ellis Horwood series in artificial intelligence
Source coding algorithms for fast data compression.
Source coding algorithms for fast data compression.
Optimal hardware and software arithmetic coding procedures for the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Probability estimation for the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Software implementation of the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
A multi-purpose VLSI chip for adaptive data compression of bilevel images
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
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IBM Systems Journal
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Document Image Coding for Processing and Retrieval
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Context-based compression of binary images in parallel
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High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression
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New arithmetic coder/decoder architectures based on pipelining
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DCC '01 Proceedings of the Data Compression Conference
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ICDAR '03 Proceedings of the Seventh International Conference on Document Analysis and Recognition - Volume 1
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
The continuing evolution of advanced function printing
IBM Systems Journal
Optimal hardware and software arithmetic coding procedures for the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Probability estimation for the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Software implementation of the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
A multi-purpose VLSI chip for adaptive data compression of bilevel images
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Data compression technology in ASlC cores
IBM Journal of Research and Development
Performance as a function of compression
IBM Journal of Research and Development
IBM Journal of Research and Development
The IBM JBIG-ABIC verification suite
IBM Journal of Research and Development
A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC
Journal of Signal Processing Systems
Modeling the Quantizer Behavior of Subbands for Data Rate Limitations in JPEG2000
MMM '09 Proceedings of the 15th International Multimedia Modeling Conference on Advances in Multimedia Modeling
An efficient VLSI architecture for CBAC of AVS HDTV decoder
Image Communication
Efficient implementation techniques for maximum likelihood-based error correction for JPEG2000
IEEE Transactions on Circuits and Systems for Video Technology
Transparent and perceptually enhanced JPEG image encryption
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Design and implementation of JPEG2000 arithmetic decoder based on Handel-C
ASID'09 Proceedings of the 3rd international conference on Anti-Counterfeiting, security, and identification in communication
Titan-R: A Multigigabit Reconfigurable Combined Compression/Decompression Unit
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A novel pipeline design for H.264 CABAC decoding
PCM'07 Proceedings of the multimedia 8th Pacific Rim conference on Advances in multimedia information processing
A high performance MQ encoder architecture in JPEG2000
Integration, the VLSI Journal
Speeding up Dirac's entropy coder
MIV'05 Proceedings of the 5th WSEAS international conference on Multimedia, internet & video technologies
Complexity analysis of adaptive binary arithmetic coding software implementations
NEW2AN'11/ruSMART'11 Proceedings of the 11th international conference and 4th international conference on Smart spaces and next generation wired/wireless networking
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000
Integration, the VLSI Journal
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The Q-Coder is a new form of adaptive binary arithmetic coding. The binary arithmetic coding part of the technique is derived from the basic concepts introduced by Rissanen, Pasco, and Langdon, but extends the coding conventions to resolve a conflict between optimal software and hardware implementations. In addition, a robust form of probability estimation is used in which the probability estimate is derived solely from the interval renormalizations that are part of the arithmetic coding process. A brief tutorial of arithmetic coding concepts is presented, followed by a discussion of the compatible optimal hardware and software coding structures and the estimation of symbol probabilities from interval renormalization.