Data compression using dynamic Markov modelling
The Computer Journal
Text compression
Practical dictionary management for hardware data compression
Communications of the ACM
An empirical evaluation of coding methods for multi-symbol alphabets
Information Processing and Management: an International Journal - Special issue: data compression
Performance optimization of wireless local area networks through VLSI data compression
Wireless Networks - Special issue VLSI in wireless networks
Evolvable hardware chip for high precision printer image compression
AAAI '98/IAAI '98 Proceedings of the fifteenth national/tenth conference on Artificial intelligence/Innovative applications of artificial intelligence
Gbit/s lossless data compression hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
An overview of the basic principles of the Q-Coder adaptive binary arithmetic coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
IBM Journal of Research and Development
Titan II: An IPcomp Processor for 10-Gbps Networks
IEEE Design & Test
An introduction to arithmetic coding
IBM Journal of Research and Development
IEEE Transactions on Signal Processing - Part II
An adaptive multialphabet arithmetic coding for video compression
IEEE Transactions on Circuits and Systems for Video Technology
| Hi-index | 0.00 |
Data compression techniques can alleviate bandwidth problems in even multigigabit networks and are especially useful when combined with encryption. This article demonstrates a reconfigurable hardware compressor/decompressor core, the Titan-R, which can compress/decompress data streams at 8.5 Gb/sec, making it the fastest reconfigurable such device ever proposed; the presented full-duplex implementation allows for fully symmetric compression and decompression rates at 8.5 Gbps each. Its compression algorithm is a variation of the most widely used and efficient such scheme, the Lempel-Ziv (LZ) algorithm that uses part of the previous input stream as the dictionary. In order to support this high network throughput, the Titan-R utilizes a very fine-grained pipeline and takes advantage of the high bandwidth provided by the distributed on-chip RAMs of state-of-the-art FPGAs.