A locally adaptive data compression scheme
Communications of the ACM
Data compression using dynamic Markov modelling
The Computer Journal
Text compression
Practical dictionary management for hardware data compression
Communications of the ACM
An empirical evaluation of coding methods for multi-symbol alphabets
Information Processing and Management: an International Journal - Special issue: data compression
Performance optimization of wireless local area networks through VLSI data compression
Wireless Networks - Special issue VLSI in wireless networks
The Data Compression Book
How Much Logic Should Go in an FPGA Logic Block?
IEEE Design & Test
An overview of the basic principles of the Q-Coder adaptive binary arithmetic coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
IBM Journal of Research and Development
An adaptive multialphabet arithmetic coding for video compression
IEEE Transactions on Circuits and Systems for Video Technology
Titan II: An IPcomp Processor for 10-Gbps Networks
IEEE Design & Test
A Cost-Effective Main Memory Organization for Future Servers
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
A case for multi-level main memory
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
A Robust Main-Memory Compression Scheme
Proceedings of the 32nd annual international symposium on Computer Architecture
Hardware implementation of hierarchical FSMs
WISICT '05 Proceedings of the 4th international symposium on Information and communication technologies
A lossless data compression and decompression algorithm and its hardware architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy and performance evaluation of lossless file data compression on server systems
SYSTOR '09 Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference
A trace-capable instruction cache for cost efficient real-time program trace compression in SoC
Proceedings of the 46th Annual Design Automation Conference
Real-time lossless compression for silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Titan-R: A Multigigabit Reconfigurable Combined Compression/Decompression Unit
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
C-pack: a high-performance microprocessor cache compression algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UPaRC: ultra-fast power-aware reconfiguration controller
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents the X-MatchPRO high-speed lossless data compression algorithm and its hardware implementation, which enables data independent throughputs of 1.6 Gbit/s compression and decompression using contemporary low-cost reprogrammable field-programmable gate array technology. A full-duplex implementation is presented that allows a combined compression and decompression performance of 3.2 Gbit/s. The features of the compression algorithm and architecture that have enabled the high throughputs are described in detail. A comparison between this device and other commercially available data compressors is made in terms of technology, compression ratio, and throughput. X-MatchPRO is a fully synchronous design proven in silicon specially targeted to improve the performance of Gbit/s storage and communication applications.