New arithmetic coder/decoder architectures based on pipelining

Authors:
R. R. Osorio;J. D. Bruguera
Affiliations:
-;-
Venue:
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Year:
1997

Citing 4
Cited 0

Arithmetic coding for data compression

Communications of the ACM
An overview of the basic principles of the Q-Coder adaptive binary arithmetic coder

IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
A multi-purpose VLSI chip for adaptive data compression of bilevel images

IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
An introduction to arithmetic coding

IBM Journal of Research and Development

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we present new VLSI architectures for the arithmetic encoding and decoding of multilevel images. In these algorithms the speed is limited by their recursive natures and the arithmetic and memory access operations. They become specially critical in the case of decoding. In order to reduce the cycle length we propose working with two executions of the algorithm which alternate in the use of the pipelined hardware with a minimum increase in its cost.