PANDA: Processing algorithm for noncoded document acquisition
IBM Journal of Research and Development
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Source coding algorithms for fast data compression.
Source coding algorithms for fast data compression.
An overview of the basic principles of the Q-Coder adaptive binary arithmetic coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Optimal hardware and software arithmetic coding procedures for the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Probability estimation for the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Software implementation of the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
ImagePlus high performance transaction system
IBM Systems Journal
Practical dictionary management for hardware data compression
Communications of the ACM
A fast, highly reliable data compression chip and algorithm for storage systems
IBM Journal of Research and Development
New arithmetic coder/decoder architectures based on pipelining
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Quadtree based JBIG compression
DCC '95 Proceedings of the Conference on Data Compression
An overview of the basic principles of the Q-Coder adaptive binary arithmetic coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Optimal hardware and software arithmetic coding procedures for the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Probability estimation for the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Data compression technology in ASlC cores
IBM Journal of Research and Development
A JBIG-ABIC compression engine for digital document processing
IBM Journal of Research and Development
Performance as a function of compression
IBM Journal of Research and Development
IBM Journal of Research and Development
The IBM JBIG-ABIC verification suite
IBM Journal of Research and Development
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A VLSI chip for data compression has been implemented based on a general-purpose adaptive binary arithmetic coding (ABAC) architecture. This architecture permits the reuse of adapter and arithmetic coder logic in a universal way, which together with application-specific model logic can create a variety of powerful compression systems. The specific version of the adapter/coder used herein is the "Q-Coder," described in various companion papers. The hardware implementation is in a single HCMOS chip, to maximize speed and minimize cost. The primary purpose of the chip is to provide superior data compression performance for bilevel image data by using conditional binary source models together with adaptive arithmetic coding. The coding scheme implemented is called the Adaptive Bilevel Image Compression (ABIC) algorithm. On business documents, it consistently outperforms such nonadaptive algorithms as the CCITT Group 4 (T.6) Standard and comes into its own when adapting to documents scanned at different resolutions or which include significantly different data such as digital halftones. The multi-purpose nature of the chip allows access to internal partition combinations such as the "Q" adapter/coder, which in combination with external logic can be used to realize hardware for other compression applications. On-chip memory limitations can also be overcome by the addition of external memory in special cases. Other options include the uploading and downloading of adaptive statistics and choices to encode or decode, with or without adaptation of these statistics.