The IBM JBIG-ABIC verification suite

Authors:
P. S. Colyer;J. L. Mitchell
Affiliations:
IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont;IBM Research Division, Thomas J. Watson Research Center, P. O. Box 218, Yorktown Heights, New York
Venue:
IBM Journal of Research and Development
Year:
1998

Citing 7
Cited 1

PANDA: Processing algorithm for noncoded document acquisition

IBM Journal of Research and Development
JPEG Still Image Data Compression Standard

JPEG Still Image Data Compression Standard
An overview of the basic principles of the Q-Coder adaptive binary arithmetic coder

IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
Software implementation of the Q-Coder

IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
A multi-purpose VLSI chip for adaptive data compression of bilevel images

IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
A JBIG-ABIC compression engine for digital document processing

IBM Journal of Research and Development
The Qx-coder

IBM Journal of Research and Development

Data compression technology in ASlC cores

IBM Journal of Research and Development

Quantified Score

Hi-index	0.00

Visualization

Abstract

The IBM JBIG-ABIC Verification Suite is a newly designed verification suite that contains more than 5000 correctly encoded test images. Previously existing verification images in total and consolidated in an ad hoc suite tested only a small fraction of the algorithm and were inadequate. The IBM JBIG-ABIC Verification Suite provides compatibility testing reference data for the ITU-T/ISO JBIG sequential mode and IBM ABIC image compression standards. In this paper, the test images are described and related to the JBIG and ABIC compression standards and options. The verification suite was used to debug and verify the algorithms in the IBM JBIG-ABIC core that is integrated into the Xionics XipChip imaging microcontrollers.