A new data structure for cumulative frequency tables
Software—Practice & Experience
Arithmetic coding for data compression
Communications of the ACM
A programming environment for the design of complex high speed ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
A byte-wise normalization method in arithmetic coding
Software—Practice & Experience
A Scalable Architecture for MPEG-4 Wavelet Quantization
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
High Performance Arithmetic Coding for Small Alphabets
DCC '97 Proceedings of the Conference on Data Compression
An overview of the basic principles of the Q-Coder adaptive binary arithmetic coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
VLSI architecture of arithmetic coder used in SPIHT
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In state-of-the-art multimedia compression standards, arithmetic coding is widely used as a powerful entropy compression method. In the MPEG-4 standard a specific 4-symbol, multiple-context arithmetic coder is used for wavelet based image compression. In this paper we present a first-of-a-kind architecture capable of processing close to 1 symbol per cycle, managing multiple context in a simple, yet cost-efficient manner. We explain the need for such an architecture, develop the algorithm and propose an efficient implementation. The characteristics of the architecture are detailed and a comparison with other alternatives is presented. This architecture has been synthesized achieving a maximum speed of 170 MHz, equivalent to 340 Mbits/s.