Arithmetic coding for data compression
Communications of the ACM
A Scalable Architecture for MPEG-4 Wavelet Quantization
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression
Journal of VLSI Signal Processing Systems
FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A JBIG-ABIC compression engine for digital document processing
IBM Journal of Research and Development
VLSI Implementation of a Modified Efficient SPIHT Encoder
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Efficient FPGA implementation of DWT and modified SPIHT for lossless image compression
Journal of Systems Architecture: the EUROMICRO Journal
SPIHT image compression without lists
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 04
Advances in Engineering Software
IBM Journal of Research and Development
Generalized kraft inequality and arithmetic coding
IBM Journal of Research and Development
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Line-based, reduced memory, wavelet image compression
IEEE Transactions on Image Processing
High performance scalable image compression with EBCOT
IEEE Transactions on Image Processing
A new, fast, and efficient image codec based on set partitioning in hierarchical trees
IEEE Transactions on Circuits and Systems for Video Technology
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard
IEEE Transactions on Circuits and Systems for Video Technology
SPIHT image compression on FPGAs
IEEE Transactions on Circuits and Systems for Video Technology
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A high-throughput memory-efficient arithmetic coder architecture for the set partitioning in hierarchical trees (SPIHT) image compression is proposed based on a simple context model in this paper. The architecture benefits from various optimizations performed at different levels of arithmetic coding from higher algorithm abstraction to lower circuits' implementations. First, the complex context model used by software is mitigated by designing a simple context model, which just uses the brother nodes' states in the coding zerotree of SPIHT to form context symbols for the arithmetic coding. The simple context model results in a regular access pattern during reading the wavelet transform coefficients, which is convenient to the hardware implementation, but at a cost of slight performance loss. Second, in order to avoid rescanning the wavelet transform coefficients, a breadth first search SPIHT without lists algorithm is used instead of SPIHT with lists algorithm. Especially, the coding bit-planes of each zero tree are processed in parallel. Third, an out-of-order execution mechanism for different types of context is proposed that can allocate the context symbol to the idle arithmetic coding core with a different order that of the input. For the balance of the input rate of the wavelet coefficients, eight arithmetic coders are replicated in the compression system. And in one arithmetic coder, there exists four cores to process different contexts. Fourth, several dedicated circuits are designed to further improve the throughput of the architecture. The common bit detection (CBD) circuit is used for unrolling the renormalization stage of the arithmetic coding. The carry look-ahead adder (CLA) and fast multiplier-divider are also employed to shorten the critical path in the architecture. Moreover, an adaptive clock switch mechanism can stop some invalid bit-planes' clock for the power saving purpose according to the input images. Experimental results demonstrate that the proposed architecture attains a throughput of 902.464 Mb/s at its maximum and achieves savings of 20.08% in power consumption over full bit-planes coding scheme based on field-programmable gate arrays (FPGAs).