Arithmetic coding for data compression
Communications of the ACM
The Data Compression Book
A Corpus for the Evaluation of Lossless Compression Algorithms
DCC '97 Proceedings of the Conference on Data Compression
A JBIG-ABIC compression engine for digital document processing
IBM Journal of Research and Development
Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
VLSI architecture of arithmetic coder used in SPIHT
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a hardware implementation of an adaptive modelling unit for parallel binary arithmetic coding. The presented model combines the advantages of binary arithmetic coding where the coding process is simplified, with the benefits of multi-alphabet arithmetic coding where any type of data can be compressed. The modelling unit adopts a simple method to store and modify the information, making it able to process 8 bits per clock cycle and to increase substantially the arithmetic coding speed. This model has been implemented in an A500K130 ProASIC FPGA and offers a throughput of 256 Mbits/s.