Static scheduling techniques for dependent tasks on dynamically reconfigurable devices
Journal of Systems Architecture: the EUROMICRO Journal
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
A General-Purpose FPGA-Based Reconfigurable Platform for Video and Image Processing
ISNN 2009 Proceedings of the 6th International Symposium on Neural Networks: Advances in Neural Networks - Part III
Progressive sharing for a secret image
Journal of Systems and Software
Wavelet compression with set partitioning for low bandwidth telemetry from AUVs
Proceedings of the Fifth ACM International Workshop on UnderWater Networks
Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression
ACM Transactions on Embedded Computing Systems (TECS)
A Novel VLSI Architecture of SPIHT Using Breadth First Search for Real-Time Applications
Journal of Signal Processing Systems
VLSI architecture of arithmetic coder used in SPIHT
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present an implementation of the image compression routine set partitioning in hierarchical trees (SPIHT) in reconfigurable logic. A discussion on why adaptive logic is required, as opposed to an application specific integrated circuit (ASIC), is provided along with background material on the image compression algorithm. We analyzed several discrete wavelet transform (DWT) architectures and selected the folded DWT design. In addition we provide a study on what storage elements are required for each wavelet coefficient. A modification to the original SPIHT algorithm is implemented to parallelize the computation. The architecture of our SPIHT engine is based upon fixed-order SPIHT, developed specifically for use within adaptive hardware. For an N×N image fixed-order SPIHT may be calculated in N2/4 cycles. Square images which are powers of 2 up to 1024×1024 are supported by the architecture. Our system was developed on an Annapolis Microsystems WildStar board populated with Xilinx Virtex-E parts. The system achieves a 450× speedup versus a microprocessor solution, with less than a 0.2-db loss in peak signal-to-noise ratio over traditional SPIHT.