A Fast and Low Complexity Image Codec based on Backward Coding of Wavelet Trees
DCC '06 Proceedings of the Data Compression Conference
Embedded image coding using zerotrees of wavelet coefficients
IEEE Transactions on Signal Processing
Line-based, reduced memory, wavelet image compression
IEEE Transactions on Image Processing
IEEE Transactions on Image Processing
High performance scalable image compression with EBCOT
IEEE Transactions on Image Processing
A new, fast, and efficient image codec based on set partitioning in hierarchical trees
IEEE Transactions on Circuits and Systems for Video Technology
SPIHT image compression on FPGAs
IEEE Transactions on Circuits and Systems for Video Technology
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A bit-plane parallel architecture for a modified set partitioning in hierarchical trees (SPIHT) without lists algorithm, which uses breadth first search scheme, is proposed. The breadth first search scheme is suitable for very large scale integration (VLSI) implementation based on the analysis of SPIHT algorithm. The architecture has advantages of high parallelism, no intermediate buffer as a single tree is scanned. After field programmable gate arrays (FPGAs) synthesis and simulation, the throughput of the proposed architecture can reach 60 MSample/Sec. As the breadth first search scheme is very similar to that of SPIHT with lists, the quality of reconstructed images is almost the same with that of SPIHT with lists.